Digital background calibration in pipelined ADCS

ABSTRACT

Digital background calibration in a pipelined ADC is performed by extracting a capacitor mismatch value Δ that represents a mismatch between a sampling capacitor C 1  and a feedback capacitor C 2  in the pipelined ADC, and using Δ to correct the capacitor mismatch error. Δ is extracted by performing commutated feedback capacitor switching (CFCS) in a background correlation loop. The error caused by the capacitor mismatch is calibrated out by subtracting the error from a digital output D out  of the pipelined ADC. Convergence speed may be accelerated and convergence accuracy may be increased during digital background calibration of pipelined ADCs, by using a higher order LPF. A bandwidth switching scheme may be implemented by the LPF, i.e. a larger bandwidth may be utilized during calibration start-up to increase convergence speed during start-up and a smaller bandwidth may be utilized during steady state to increase convergence accuracy during steady state.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon, and claims the benefit of priority under35 U.S.C. §119(e) from U.S. Provisional Patent Application Ser. No.61/021,739 (the “'739 provisional application”), filed Jan. 17, 2008,entitled “Digital Background Calibration in Pipelined ADCs.” Thecontents of the '739 provisional application is incorporated herein byreference in its entirety as though fully set forth.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

This invention was made with government support under grant NSF/PHY06-46094, awarded by the National Science Foundation. The government hascertain rights in the invention.

BACKGROUND

A major consideration in the design of analog-to-digital converters(ADCs) is capacitor mismatch errors. Various calibration techniques tocorrect them have been developed in both analog and digital domains.Digital background calibration is one class of such techniques.

While a number of digital background calibration techniques are known orresearched, there is a need for simpler, more effective, and morecost-efficient methods for calibrating out capacitor mismatch errors.

Correlation based digital background calibration is being widely studiedas a means to mitigate component mismatch errors in pipelined ADCs.Currently, a pronounced drawback of the correlation-based digitalbackground calibration is slow convergence. With reasonable calibrationcircuit cost, it typically takes several 10 T samples for thecalibration to converge within 12-bit accuracy. A higher resolutionrequires even more samples.

There is a need for methods and systems that can accelerate convergencein correlation based digital background calibration, without sacrificingconvergence accuracy.

SUMMARY

In one embodiment, digital background calibration in a pipelined ADC isperformed by extracting a capacitor mismatch value Δ that represents theamount of capacitor mismatch in the pipelined ADC, and using theextracted value Δ to determine the error caused by the capacitormismatch. In one embodiment, the capacitor mismatch value Δ is extractedby performing commutated feedback capacitor switching in a backgroundcorrelation loop. The error caused by the capacitor mismatch is thencalibrated out, by subtracting the error from a digital output D_(out)of the pipelined ADC.

In one embodiment, convergence speed is accelerated and convergenceaccuracy is increased during digital background calibration of pipelinedADCs, by using a higher order LPF (low pass filter) with a bandwidthswitching scheme that utilizes a larger bandwidth during calibrationstart-up and a smaller bandwidth during steady state to accelerateconvergence speed and increase convergence accuracy during steady state.

BRIEF DESCRIPTION OF DRAWINGS

The drawing figures depict one or more implementations in accord withthe present concepts, by way of example only, not by way of limitations.The drawings disclose illustrative embodiments. They do not set forthall embodiments. Other embodiments may be used in addition or instead.In the figures, like reference numerals refer to the same or similarelements.

FIGS. 1( a) and 1(b) illustrate two different operational phases of theMSB (Most Significant Bit) stage of a 1-bit-per-stage pipelined ADC,namely the sampling phase (FIG. 1( a)) and the charge transfer phase(FIG. 1( b)).

FIG. 1( c) illustrates the ADC transfer curve for a 1-bit-per-stagepipelined ADC.

FIG. 2( a) illustrates CFCS (commutated feedback capacitor switching)applied during the charge transfer phase.

FIG. 2( b) is a plot of the ADC transfer curve, D_(out) versus V_(in).

FIG. 3( a) illustrates a first mode of executing CFCS, CFCS-A, in a1-bit-per-stage pipelined ADC.

FIG. 3( b) illustrates a second mode of executing CFCS, CFCS-B, in a1-bit-per-stage pipelined ADC.

FIG. 3( c) illustrates the ADC transfer curves for CFCS-A and CFCS-B,for Δ>0.

FIG. 4 illustrates an architecture and discrete-time signal processingfor a digital background calibration in accordance with one embodimentof the present disclosure.

FIG. 5( a) illustrates CFCS-A for a 1.5-bit-per-stage case. FIG. 5( b)illustrates CFCS-B for a 1.5-bit-per-stage case. FIG. 5( c) illustratestransfer curves for CFCS-A and CFCS-B for Δ>0.

FIG. 6 is a schematic block diagram of a general correlation baseddigital background correlation.

FIG. 7 illustrates PSDs (power spectral densities) of Φ_(VV)(e^(jω)),Φ_(XX)(e^(jω)) and Φ_(YY)(e^(jω)).

FIG. 8 illustrates a frequency-domain representation (log scale) ofΔ_(in)[n].

FIG. 9 illustrates a 3rd order discrete-time IIR LPF (infinite impulseresponse low-pass filter) that incorporates a bandwidth switchingscheme, in accordance with one embodiment of the present disclosure.

DETAILED DESCRIPTION I. CFCS Based Digital Background Calibration inPipelined ADCS

In the present disclosure, CFCS (commutated feedback capacitorswitching) is used in cooperation with correlation-based digitalbackground calibration to extract capacitor mismatch information, whichis then used to correct the mismatch errors. The approach described inthe present disclosure adds minimal digital cost, yielding anarchitecture much simpler than many existing digital backgroundcalibration approaches. This all-digital technique requires minimalextra digital circuits, and is applicable to single-bit andmulti-bit-per-stage architectures. Also, the digital backgroundcalibration systems and methods described in the present disclosureconverge for any input amplitudes.

FIGS. 1( a) and (b) show two different operational phases of themost-significant-bit (MSB) stage, in a standard 1-bit-per-stagepipelined ADC 100. In one embodiment, capacitor mismatches may beassumed only in the most-significant-bit (MSB) stage, for simplicity. Inthe illustrated embodiment, the pipelined ADC includes two capacitors,C₁ (shown with reference numeral 110) and C₂ (shown with referencenumeral 120), and a comparator 140. Ideally, C₁ and C₂ would be thesame, but mismatches exist between them in reality. The mismatch betweenC₁ and C₂ may be represented with a parameter Δ, defined as Δ≡(C₁/C₂)−1.

In the sampling phase (illustrated in FIG. 1( a)), the ADC's inputvoltage V_(in) sampled and held on C₁ and C₂ is compared to voltage zeroto make decision on the MSB, d₁.

In the subsequent charge transfer phase (illustrated in FIG. 1( b)),V_(REF) or −V_(REF) will be connected to C₁ according to d₁, and thetotal charge will be redistributed between C₁ and C₂, resulting in thefollowing residue voltage V_(RES):

$\begin{matrix}{V_{RES} = \left\{ \begin{matrix}{{\left( {2 + \Delta} \right)V_{in}} + {\left( {1 + \Delta} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\{{\left( {2 + \Delta} \right)V_{in}} - {\left( {1 + \Delta} \right){V_{REF}\mspace{14mu}\left\lbrack {{{for}\mspace{20mu} d_{1}} = 1} \right\rbrack}}}\end{matrix} \right.} & (1)\end{matrix}$

V_(RES) is now an input to the following stage, which generates thesecond-significant bit, d₂. Repeating this procedure, V_(in) isconverted to a set of digitized bits, {d₁, d₂, d₃, . . . d_(N)}, where Nis the total number of stages in the pipelined ADC. This set of bits isthe digital output of the ADC, or alternatively, the representation ofthe ADC's digital output can be thought of as:

$D_{out} = {{- V_{REF}} + {2V_{REF}{\sum\limits_{i = 1}^{n}\left( {d_{i}2^{- i}} \right)}}}$

Using equation (1), D_(out) can be related to V_(in) via:

$\begin{matrix}{D_{out} = \left\{ \begin{matrix}{{\left( {1 + {\Delta/2}} \right)V_{in}} + {\left( {\Delta/2} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\{{\left( {1 + {\Delta/2}} \right)V_{in}} - {\left( {\Delta/2} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{20mu} d_{1}} = 1} \right\rbrack}}}\end{matrix} \right.} & (2)\end{matrix}$

In the above equation, quantization noise terms to highlight capacitormismatch effects.

FIG. 1( c) is a plot of the ADC transfer curve, D_(out) versus V_(in),in accordance with equation (2). In the absence of capacitor mismatch(Δ=0), the transfer curve is a straight line. Capacitor mismatch (Δ≠0)creates a discontinuity in the transfer curve, shown as wide code inFIG. 1( c), causing differential nonlinearity (DNL).

To solve the DNL problem, it is known to apply commutated feedbackcapacitor switching (CFCS). FIGS. 2( a)-2(b) illustrate the applying ofcommutated feedback capacitor switching (CFCS) to remove DNL, in apipelined ADC having a first capacitor C₁ (shown in with referencenumeral 210), a second capacitor C₂ (shown with reference numeral 220),and a comparator 240. CFCS may be applied during the charge transferphase, as shown in FIG. 2( a). If d₁=0, C₁ is selected as a feedbackcapacitor. If d₁=1, C₂ is selected as a feedback capacitor.

The essence of CFCS is the selection of the feedback capacitor in thecharge transfer phase based on d₁ determined in the prior samplingphase. CFCS alters the expression for the residue voltage of the MSBstage from equation (1) above to the following:

$\begin{matrix}{V_{RES} = \left\{ \begin{matrix}{{\left( {2 - \Delta} \right)V_{in}} + {\left( {1 - \Delta} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\{{\left( {2 + \Delta} \right)V_{in}} - {\left( {1 + \Delta} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{20mu} d_{1}} = 1} \right\rbrack}}}\end{matrix} \right.} & (3)\end{matrix}$

Subsequently, the ADC output D_(out) is related to V_(in), via:

$\begin{matrix}\begin{matrix}{D_{out} = \left\{ \begin{matrix}{{\left( {1 - {\Delta/2}} \right)V_{in}} - {\left( {\Delta/2} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\{{\left( {1 + {\Delta/2}} \right)V_{in}} - {\left( {\Delta/2} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{20mu} d_{1}} = 1} \right\rbrack}}}\end{matrix} \right.} \\{= {V_{in} + {\left( {\Delta/2} \right)\left( {{V_{in}} - V_{REF}} \right)}}}\end{matrix} & (4)\end{matrix}$

where in the simplification into the last line, the fact that V_(in)>0for d₁=1 and V_(in)<0 for d₁=0 has been used.

FIG. 2( b) is a plot of the ADC transfer curve, D_(out) versus V_(in).As seen in FIG. 2( b), the discontinuity of the transfer curve has nowdisappeared, hence removing DNL.

In some embodiments of the present disclosure, CFCS is used for adifferent purpose, namely to extract the capacitor mismatch information,with the help of a background digital-correlation loop. The extractedmismatch information is subsequently used to calibrate out errors causedby the mismatch. This approach can improve ADC performance (includingbut not limited to resolution, and integral nonlinearity), beyond whatcan be achieved by removal of DNL only.

1-Bit-Per-Stage Case

A starting point for the extraction of capacitor mismatch informationusing CFCS, described in the present disclosure, may be the realizationthat there are two ways of executing CFCS in 1-bit-per-stage pipelinedADCs. The first way, described above, is to select C₁ as a feedbackcapacitor if d₁=0, and to select C₂ as a feedback capacitor if d₁=1. Inthe present disclosure, this specific CFCS execution (which led toequation (4) above) is hereinafter referred to as “CFCS-A” or “firstCFCS mode.” CFCS-A (or “first CFCS mode”), executed in a 1 bit-per-stagepipelined ADC, previously illustrated in FIG. 2( a), is re-illustratedin FIG. 3( a), which shows a pipelined ADC having a first capacitor C₁(shown with reference numeral 310), a second capacitor C₂ (shown withreference numeral 320), and a comparator 340.

The other way is to select C₂ as a feedback capacitor for d₁=0 and toselect C₁ as a feedback capacitor for d₁=1. In the present disclosure,this CFCS execution is referred to as “CFCS-B” or “second CFCS mode.”and is illustrated in FIG. 3( b). FIG. 3( b) illustrates the second CFCSmode, or CFCS-B, in a 1-bit-per-stage pipelined ADC.

For CFCS-B, V_(RES) is given by:

$\begin{matrix}{V_{RES} = \left\{ \begin{matrix}{{\left( {2 + \Delta} \right)V_{in}} + {\left( {1 + \Delta} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\{{\left( {2 - \Delta} \right)V_{in}} - {\left( {1 - \Delta} \right){V_{REF}\mspace{20mu}\left\lbrack {{{for}\mspace{20mu} d_{1}} = 1} \right\rbrack}}}\end{matrix} \right.} & (5)\end{matrix}$

and accordingly, D_(out) is related to V_(in) via:D _(out) =V _(in)−(Δ/2)(|V _(in) |−V _(REF))  (6).

FIG. 3( c) illustrates the ADC transfer curves for CFCS-A and CFCS-B,for Δ>0. As seen in FIG. 3( c), and evident from equations (4) and (6)above, CFCS-A and CFCS-B lead to different ADC transfer characteristics.For the same analog input V_(in), the digital output D_(out) of CFCS-Ais always smaller than CFCS-B for Δ>0, and vice versa for Δ<0. Thedistance between the two transfer curves is proportional to Δ, as can beseen by subtracting (4) from (6):D _(out,A) −D _(out,B)=Δ·(|V _(in) |−V _(REFs))  (7),

where in equation (7) above, subscripts A and B indicate use of CFCS-Aand CFCS-B, respectively.

Δ may be expressed as:

$\begin{matrix}{\Delta \approx \frac{D_{{out},_{A}} - D_{{out},_{B}}}{{D_{{out},_{A}}} - V_{REF}}} & (8)\end{matrix}$

In going from equation (7) to equation (8), |V_(in)| was approximatedwith |D_(out,A)| to express Δ in terms of digital quantities that areknown at the ADC output. Alternatively, |V_(in)| may be replaced with|D_(out,B)|. The difference between |D_(out,A)| and |D_(out,B)| in thedenominator adds only a second-order effect in the expression of Δ.

Equation (8) shows that by measuring the distance D_(out.A)−D_(out.B)between the transfer curves for CFCS-A and CFCS-B for any input V_(in),the capacitor mismatch information Δ can in principle be extracted.

In practice, D_(out.A) and D_(out.B) cannot be obtained simultaneously,for a given input V_(in). This may be done if there were two identicalADCs, and operated one with CFCS-A and the other with CFCS-B, but suchan arrangement is not possible. Therefore, extraction of Δ directlyusing (8) is not practically feasible. Instead, a time-averaged versionof (7) or (8) may be obtained to extract Δ. This may be done in a givenADC first by randomly choosing one CFCS mode between CFCS-A or CFCS-Bwith equal probability for each input sample, then by creating a datasequence consisting of the resulting ADC outputs but with each outputmultiplied by 1 if CFCS-A was used and by −1 if CFCS-B was used, andthen by time-averaging (i.e. low-pass filtering) the data sequence. Thisprocedure to extract Δ can be executed by a correlation-based digitalbackground calibration loop shown in FIG. 4.

FIG. 4 illustrates an architecture and discrete-time signal processingfor a digital background calibration, i.e. illustrates a system 400 forbackground calibration of a pipelined ADC in accordance with oneembodiment of the present disclosure. Again for simplicity, in theembodiment illustrated in FIG. 4 capacitor mismatches are assumed onlyin the MSB stage, and hence in FIG. 4 the calibration is performed onlyin the MSB stage. In other embodiments of the present disclosure,capacitor mismatches may be assumed in stages other than the MSB stage,and the techniques described below may also be used to calibratecapacitor mismatch errors in stages other than the MSB stage.

In overview, the system 400 may include a pseudo-random number generator410 configured to generate a pseudo-random variable X[n], where n is thenumber of input samples to the ADC; an analog-to-digital conversionmodule 430 configured to generate a pre-calibration ADC outputD_(out)[n] from an analog input voltage V_(in) of the pipelined ADC; a Δextraction module 450 configured to process the variable X[n] and theoutput D_(out)[n] to extract the value Δ of the mismatch between C₁ andC₂, the Δextraction module including a discrete-time infinite impulseresponse low-pass filter (IIR LPF) 452 configured to output a DC averageof X[n] D_(out)[n]; and a digital calibration module 460 configured toreceive as input the capacitor mismatch value Δ and the pre-calibrationoutput D_(out)[n], and to calibrate the output D_(out)[n] by subtractingtherefrom the error caused by the capacitor mismatch value Δ.

Switching between CFCS-A and CFCS-B in the MSB stage is controlled by apseudo-random variable X[n], which in the illustrated embodiment assumes+1 and −1 with equal probability. When X[n]=1, CFCS-A is executed, andADC output D_(out,A) of equation (4) results; when X[n]=−1, the MSBstage executes CFCS-B, yielding ADC output D_(out.B) of (6). Equations(4) and (6) may actually be combined into one equation, noting X[n]=1for CFCS-A and X[n]=−1 for CFCS-B:D _(out) [n]=V _(in) [n]+X[n]·(Δ/2)(|V _(in) [n]|−V _(REF))  (9).

The above pre-calibration ADC output with the error term, X[n](Δ/2)(|V_(in)[n]−V_(REF)|), regarding which the goal is to calibrate outeventually, may now be separated into calibration path P1 and capacitormismatch information extraction path P2, both of which are shown in FIG.4.

Focusing on P2, D_(out)[n] is first multiplied by X[n], subsequentlymultiplied by a certain function of D_(out)[n], f(D_(out)[n], and thengoes through a Δ-extraction block. For 1-bit-per-stage pipelined ADCs,f(D_(out)[n])=1 is used. This signal processing yields the followingsignal at the input of the Δ-extraction block of FIG. 4:

$\begin{matrix}{{{X\lbrack n\rbrack}{D_{out}\lbrack n\rbrack}} = {{{X\lbrack n\rbrack}{V_{in}\lbrack n\rbrack}} + {\frac{\Delta}{2}{\left( {{{V_{in}\lbrack n\rbrack}} - V_{REF}} \right).}}}} & (10)\end{matrix}$

The Δ-extraction block is a discrete-time infinite impulse response lowpass filter (IIR LPF) 452, and outputs a DC average of the input signalin equation (10). Since X[n] is a pseudo-random signal taking ±1 and isnot correlated to V_(in)[n], the DC average of the first term ofequation (10) is zero. In contrast, the second term of (10) is alwayspositive or negative, for |V_(in)[n]|≦V_(REF), and has a non-zero DCcomponent. Therefore, at the output of the Δ extraction block (IIR LPF)one attains:

$\begin{matrix}{\overset{\_}{{X\lbrack n\rbrack}{D_{out}\lbrack n\rbrack}} = {\frac{\Delta}{2}{\left( {\overset{\_}{{V_{in}\lbrack n\rbrack}} - V_{REF}} \right).}}} & (11)\end{matrix}$

In equation (11) above, and elsewhere in the present disclosure, theoverline signifies DC averaging. Equation (11) is a time-averagedversion of equation (7). From equation (11), Δ may be expressed as:

$\begin{matrix}{\frac{\Delta}{2} \approx \frac{\overset{\_}{{X\lbrack n\rbrack}{D_{out}\lbrack n\rbrack}}}{\overset{\_}{{D_{out}\lbrack n\rbrack}} - V_{REF}}} & (12)\end{matrix}$

where |V_(in)[n]| was approximated with |D_(out)[n]|, in going fromequation (11) to equation (12), to express Δ in terms of what isexplicitly known. The difference between |V_(in)[n]| and |D_(out)[n]| inthe denominator on the right hand side produces only a second-ordereffect in the Δ expression. The numerator on the right hand side of (12)is what is measured (hence known) at the output of the Δ-extractionblock. Equation (12) is the time-averaged version of equation (8).

The procedure outlined above, with the final result shown in equation(12), describes how a background correlation loop in conjunction withCFCS can extract the Δ information.

Once Δ is determined, it can be used it to calibrate out the error termin the pre-calibration ADC output D_(out)[n] of equation (9) in astraightforward fashion, using a digital calibration block 460 in pathP1 shown in FIG. 4.

The basic operation performed by the digital calibration block 460 is:

$\begin{matrix}{\overset{\_}{D_{out}\lbrack n\rbrack} = {{{D_{out}\lbrack n\rbrack} - {{{X\lbrack n\rbrack} \cdot \left( {\Delta/2} \right)}\left( {{{D_{out}\lbrack n\rbrack}} - V_{REF}} \right)}}\mspace{20mu} \approx {V_{in}\lbrack n\rbrack}}} & (13)\end{matrix}$

In equation (13) above, what is subtracted from D_(out)[n] in the firstline is what is now known. In going to the second line using equation(9) for D_(out)[n], second-order effects were omitted. D_(out)represents the corrected digital output, as can be seen from FIG. 4.

1.5-Bit-Per-Stage Case

FIG. 5( a) illustrates CFCS-A for a 1.5-bit-per-stage case, while FIG.5( b) illustrates CFCS-B for a 1.5-bit-per-stage case, and FIG. 5( c)illustrates transfer curves for CFCS-A and CFCS-B for Δ>0.

In the 1.5-bit-per-stage case, illustrated in FIG. 5( a)-5(c), capacitormismatches are also assumed only in the MSB stage. Again, the MSBstage's digital decision is denoted again as d₁, which now assumes oneof 00, 01, and 10. As shown in FIGS. 5( a) and 5(b), there are twocapacitors C₁ (shown with reference numeral 510) and C₂ (shown withreference numeral 520) in the MSB stage (and any other stage), whosemismatch is again represented by Δ≡C₁/C₂−1. The comparator is shown withreference numeral 540 in FIGS. 5( a) and 5(b).

The starting point, as in the 1-bit-per-stage case, is realizing thatthere are two different ways of executing CFCS. One way (CFCS-A or firstCFCS mode) is to select C₁ as a feedback capacitor when d₁=01 and toselect C₂ as a feedback capacitor when d₁=00 or 10, as shown in FIG. 5(a). The other way (CFCS-B or second CFCS mode) is to select C₂ as afeedback capacitor when d₁=01 and to select C₁ as a feedback capacitorwhen d₁=00 or 10, as shown in FIG. 5( b).

As in the 1-bit-per-stage case, it can be shown that CFCS-A and CFCS-Bresult in two different overall transfer curves, as shown in FIG. 5( c),and that the distance between the two transfer curves is proportional toΔ. Just as in the 1-bit-per-stage case, Δ is now extracted by measuringthe distance using the architecture shown in FIG. 4.

Unlike the 1-bit-per-stage case, however, where the transfer curve forCFCS-A is always below that for CFCS-B (see FIG. 3( c); Δ>0), the twotransfer curves for CFCS-A and CFCS-B in the 1.5-bit-per-stage case havea crossover at V_(in)=D_(out)=0 and D_(out,A)[n]>D_(out,B)[n] forV_(in)[n]>0 but D_(out,A)[n]<D_(out,B)[n] for V_(in)[n]<0, as shown inFIG. 5( c).

Therefore, if f(D_(out)[n])=1 is used as in the 1-bit-per-stage case,the resultant signal X[n] D_(out)[n] (X[n]=1 for CFCS-A; X[n]=−1 forCFCS-B) at the input of the Δ-extraction block of FIG. 4 will betime-averaged to zero at the output of the Δ-extraction block, no matterwhat the value of Δ is. Therefore with f(D_(out)[n])=1, Δ cannot beextracted.

This problem may be solved by using f(D_(out)[n]) specifically defined,for the 1.5-bit-per-stage case, as the following:

$\begin{matrix}{{f\left( {D_{out}\lbrack n\rbrack} \right)} = \left\{ \begin{matrix}{+ 1} & {{{if}\mspace{14mu}{D_{out}\lbrack n\rbrack}} \leq 0} \\{- 1} & {{{if}\mspace{14mu}{D_{out}\lbrack n\rbrack}} > 0.}\end{matrix} \right.} & (14)\end{matrix}$

With this f(D_(out)[n]), D_(out)[n] f(D_(out)[n]) of CFCS-A will bealways smaller than that of CFCS-B for any given V_(in)[n], and hencethe input to the Δ-extraction block in FIG. 4, namely X[n] D_(out)[n]f(D_(out)[n]), will be time-averaged to a non-zero value that isproportional to A. This shows the utility of f(D_(out)[n]), which wasless evident in the 1-bit-per-stage case.

Multi-Bit-Per-Stage Case

The background calibration technique described above can be easilygeneralized from 1-bit-per-stage and 1.5-bit-per-stage cases tom-bit-per-stage or (m+0.5)-bit-per-stage cases (m=1, 2, 3, . . . ). Inpractice, typical values for m are 1, 2, and 3.

In each stage, there are a total of 2^(m) capacitors, and again,capacitor mismatches are assumed only in the MSB stage for simplicity.The capacitors in the MSB stage are denoted as C₁, C₂, C₃, . . . C₂ ^(m)and the capacitor mismatch between C_(k), and C_(k+1) is represented asΔ_(k)≡(C_(k+1)/C_(k))−1, where k=1, 2, 3, . . . , (2^(m)−1). Once everyΔ_(k) is extracted, errors brought by all mismatches can be calibratedout.

In one embodiment, the procedure described in conjunction with FIG. 4may be used to extract Δ_(k). Two CFCS execution modes are firstdefined, which are referred to as CFCS-A_(k) (or first CFCS mode) andCFCS-B_(k) (or second CFCS mode). In CFCS-A_(k), C_(k) is selected as afeedback capacitor if d₁ is even, and C_(k+1) is selected as a feedbackcapacitor if d₁ is odd. In CFCS-B_(k), we select C_(k+1) as a feedbackcapacitor if d₁ is odd, and C_(k) is selected as a feedback capacitor ifd₁ is even.

The function f(D_(out)) is set at 1 at D_(out)=V_(in)=−V_(REF) andcontinues to be 1 with increasing V_(in), until there is a crossoverbetween the transfer curves of CFCS-A_(k) and CFCS-B_(k). At thecrossover, f(D_(out)[n]) becomes −1 and remains to be −1 until the nextcrossover. This procedure is repeated, to completely determinef(D_(out)[n]). This ensures that D_(out)[n] f(D_(out)[n]) of CFCS-A_(k)is always smaller than CFCS-B_(k) for Δ_(k), >0, and always larger thanCFCS-B_(k) for (Δ_(k)<0). From the output of the Δ-extraction blockproportional to Δ_(k), Δ_(k) is extracted.

In one embodiment, the overall calibration algorithm can be summed up asfollows, for each input sample (for each time index n):

1) Select k and decide which Δ_(k) is to be extracted, using apseudo-random signal X_(cap)[n]=1, 2, 3 . . . , (2^(m)−1)(equalprobability).

2) Select which CFCS mode to use between CFCS-A_(k) and CFCS-B_(k),according to another pseudo-random signal X_(mode)[n]=±1 (equalprobability).

3) Let X_(mode)[n]D_(out)[n]f(D_(out)[n]) go through the k^(th) LPF.From the output, Δ_(k) is extracted.

4) Perform digital calibration according to Δ_(k), obtained in step 3).

In sum, digital background calibration methods and systems have beendescribed in which CFCS is used in conjunction with backgroundcorrelation. The approach described in the present disclosure easilylends itself to the capacitor mismatch information extraction, and leadsto a very simple digital background calibration architecture, shown inFIG. 4, where the pipelined ADC is the only analog block. The cost ofimplementing the above-described techniques is low. Since X[n]=±1 andf(D_(out)[n])=±1, the two multipliers can be implemented by simplecombinational logics instead of general multipliers. Overall, only shiftregisters, standard discrete-time LPF, and simple combinational logicsare needed in the calibration loop. The architecture is much simplerthan many existing digital background calibration architectures. Incontrast to other background calibration techniques known in the art,the convergence of the techniques described above is ensured for anygiven input, with no limit on input amplitude.

II. Digital Acceleration of Correlation-Based Digital BackgroundCalibration in Pipelined ADCs

In section II of the present disclosure, a general digital technique isdescribed for accelerating convergence of correlation-based digitalbackground calibration in pipelined ADCs, implemented in someembodiments. Based on a frequency domain analysis, the componentmismatch information extraction process (a central procedure in anycorrelation-based background calibration) is first viewed asdiscrete-time low-pass filtering. This leads to a design of ahigher-order discrete-time loss-pass filter with a bandwidth switchingscheme to rapidly extract mismatch information. Simulations show thatoverall, the technique described below increases convergence speed byabout 18 times or so, in simulations, while adding minimal digital cost.

A central procedure common among all correlation-based digitalbackground calibrations is the extraction of component mismatchinformation from correlated data sequences. This extraction processdetermines convergence time.

A starting point in the simple fast-convergence solution implemented inone embodiment of the present disclosure is the realization that theextraction procedure is equivalent to discrete-time infinite impulseresponse (IIR) low-pass filtering. This notion may be attained byexamining general correlation-based calibrations in frequency domain,and showing the equivalence of a widely-used iterative extractionalgorithm to the 1^(st)-order discrete-time IIR low-pass filter (LPF).In this way, the convergence problem may be transformed into a filterdesign problem.

In overview, a first component of the fast convergence solution setforth in the present disclosure is the use of a higher-order IIR LPF,instead of the widely-used iterative extraction, which can be shown tobe equivalent to the 1^(st)-order IIR LPF, thereby acceleratingconvergence. A second component is the use of a bandwidth switchingscheme in the IIR LPF to further accelerate convergence. These twoarrangements in the digital filter for fast convergence may beimplemented with minimal added digital cost.

A frequency-domain picture of the general correlation-based digitalbackground calibration is described below. FIG. 6 is a schematic blockdiagram that illustrates an abstract model of a generalcorrelation-based digital background calibration of capacitor mismatcherrors in pipelined ADCs. In FIG. 6, the real ADC 620 is separated intoan ideal ADC 630 with no capacitor mismatch, plus the explicit capacitormismatch information, Δ. To understand Δ concretely, the example oftypical 1-bit or 1.5-bit-per-stage pipelined ADCs may be considered. Inany given stage, the mismatch between a sampling capacitor C₁ and afeedback capacitor C₂ may be represented by Δ≡|C₁/C₂−1|, and the modelof FIG. 6 may be thought of as being applied to each stage.Alternatively, Δ may be thought of as what collectively represents theoverall capacitor mismatch.

In the embodiment illustrated in FIG. 6, the calibration procedure is asfollows. First, the capacitor mismatch Δ is correlated with a causalpseudo-random signal X[n] (+1 or −1 with equal probability for n≧0; 0for n<0), generated by a pseudo random number generator 610. Thiscorrelation is added to the real ADC input, V_(in)[n]. This sum ispassed through the ideal ADC 630. As described previously, thepre-calibrated digital output of the ADC is denoted as D_(out)[n]. Asnoted in FIG. 6, D_(out)[n]=V_(in)[n]+X[n]Δ+e[n], where e[n] isquantization noise. D_(out)[n] is correlated with the same digitalpseudo-random signal X[n]. Since X²[n]=u[n], where u[n] is the unit-stepfunction, Δ·u[n]+X[n]V_(in)[n]+X[n]e[n] is attained, as the outcome ofthe second correlation. This signal (outcome of the second correction)will henceforth be denoted as Δ_(in)[n]:

$\begin{matrix}{{\Delta_{in}\lbrack n\rbrack} \equiv {{\Delta \cdot {u\lbrack n\rbrack}} + {{X\lbrack n\rbrack}{V_{in}\lbrack n\rbrack}} + {{X\lbrack n\rbrack}{{\mathbb{e}}\lbrack n\rbrack}}}\mspace{20mu} \cong {{\Delta \cdot {u\lbrack n\rbrack}} + {{X\lbrack n\rbrack}{V_{in}\lbrack n\rbrack}}}} & (15)\end{matrix}$

In the above equation, X[n]e[n] has been neglected, assuminghigh-resolution applications (>10 bits), in which V_(in)[n]>>e[n].Δ_(in)[n] bears the capacitor mismatch information, Δ, which however isobscured by the additive term, X[n]V_(in)[n]. A key step of this entireprocedure is to extract Δ from Δ_(in)[n], by effectively removing theadditive term, using a Δ extraction block. Once Δ is attained, it can beused in a standard digital calibration block 650 to calibrate outcapacitor mismatch errors from D_(out)[n], yielding the desired digitaloutput, D_(out)[n]=V_(in)[n]+e[n].

In the above model, extracting Δ within a given accuracy from Δ_(in)[n]of (15) requires a certain number of samples (the index ‘n’ runs over acertain set of integers), which defines the convergence time. Theconvergence time depends crucially on the specific extraction algorithmused. In the past, iterative methods have been used. In the presentdisclosure, a different method is proposed which is the key to a simpleand fast convergence solution implemented in some embodiments of thepresent disclosure.

The difference between the iterative algorithm, and the fast-convergencealgorithm described in the present application, is now explained. Afrequency domain picture of Δ_(in)[n] in equation (15) is firstobtained, as set forth below.

The Fourier transform of the first term of equation (15), Δ·u[n], is:

$\begin{matrix}{{\left\{ {\Delta \cdot {u\lbrack n\rbrack}} \right\}} = {{\Delta\left( {\frac{1}{1 - {\mathbb{e}}^{j\;\omega}} + {\sum\limits_{k = {- \infty}}^{\infty}{{\pi\delta}\left( {\omega + {2\pi\; k}} \right)}}} \right)}.}} & (16)\end{matrix}$

As for the second term X[n]V_(in)[n]≡Y[n] of equation (15), since it isa random process, a Fourier transform is not directly taken, but ratherits power spectral density (PSD) is calculated, and its frequency domainrepresentation is obtained by taking the square root of the PSD. To thisend, the autocorrelation functions of X[n], V_(in)[n] and Y[n] aredenoted as R_(XX)[m], R_(VV)[m], and R_(YY)[m], respectively. Since X[n]and V_(in)[n] are independent random processes,R_(VV)[m]=R_(XX)[m]·R_(YY)[m].

Suppose X[n] is a pseudo-random signal with period T: after time T, thesame pattern of X[n] is repeated. If T is large enough, R_(XX) [m] maymodeled as:

$\begin{matrix}{{R_{XX}\lbrack m\rbrack} = {{E\left\lbrack {{X\lbrack n\rbrack} \cdot {X\left\lbrack {n + m} \right\rbrack}} \right\rbrack}\mspace{20mu} \cong {\frac{1}{2}{\sum\limits_{n = {- \infty}}^{\infty}{{\delta\left\lbrack {m - {nT}} \right\rbrack}.}}}}} & (17)\end{matrix}$

In the above equation, δ[n] is the discrete-time delta function. Thismodel is approximately valid, as the correlation of two pseudo-randomsequences X[n] and X[n+m] is approximately zero (the approximate natureoriginates from the “pseudo”-randomness) if m is not an integer multipleof T, and it is exactly one half if m is an integer multiple of T andthe two sequences overlap perfectly. One half instead of one is theresult of causality, i.e., X[n]=0 for n<0.

The PSDs of X[n], V_(in)[n], and Y[n] are now denoted as Φ_(XX)(e^(jω)),Φ_(VV)(e^(jω)), and Φ_(YY)(e^(jω)), respectively. Using the WienerKhinchin theorem and equation (17), the following is obtained:

$\begin{matrix}\begin{matrix}{{\Phi_{XX}\left( {\mathbb{e}}^{j\omega} \right)} = {\left\{ {R_{XX}\lbrack m\rbrack} \right\}}} \\{{= {\frac{\pi}{T}{\sum\limits_{k = {- \infty}}^{\infty}{\delta\left( {\omega - \frac{2\pi\; k}{T}} \right)}}}},}\end{matrix} & (18)\end{matrix}$

and subsequently:

$\begin{matrix}\begin{matrix}{{\Phi_{YY}\left( {\mathbb{e}}^{j\omega} \right)} = {\left\{ {{R_{XX}\lbrack m\rbrack} \cdot {R_{VV}\lbrack m\rbrack}} \right\}}} \\{= {\frac{1}{2\pi}{\int_{- \pi}^{+ \pi}{{\Phi_{XX}\left( {\mathbb{e}}^{j\omega} \right)}{\Phi_{VV}\left( {\mathbb{e}}^{j{({\omega - \theta})}} \right)}\ {\mathbb{d}\theta}}}}} \\{= {\frac{1}{2\; T}{\sum\limits_{k = {- \frac{T}{2}}}^{\frac{T}{2}}{{\Phi_{VV}\left( {\mathbb{e}}^{j{({\omega - \frac{2\pi\; k}{T}})}} \right)}.}}}}\end{matrix} & (19)\end{matrix}$

The frequency domain illustrations of these results are shown in FIG. 7.Φ_(VV)(e^(jω)) and Φ_(XX) (e^(jω)) are shown in FIG. 7( a) and FIG. 7(b), respectively. Φ_(YY)(e^(jω)) of equation (19) is shown both in FIG.7( c), which depicts the process of scaled repeating and shifting ofΦ_(VV)(e^(jω)), and in FIG. 7( d), which depicts the final result of thetotal summation, which will be performed now.

In any practical correlation-based digital background calibration, T isalways large enough so that 2π/T is much smaller than the input signalbandwidth. Therefore, Φ_(YY)(e^(jω)) of equation (19) can be rewritteninto:

$\begin{matrix}\begin{matrix}{{\Phi_{YY}\left( {\mathbb{e}}^{j\omega} \right)} = {\left\{ {{R_{XX}\lbrack m\rbrack} \cdot {R_{VV}\lbrack m\rbrack}} \right\}}} \\{= {\frac{1}{2\pi}{\int_{- \pi}^{+ \pi}{{\Phi_{XX}\left( {\mathbb{e}}^{j\theta} \right)}{\Phi_{VV}\left( {\mathbb{e}}^{j{({\omega - \theta})}} \right)}\ {\mathbb{d}\theta}}}}} \\{= {\frac{1}{2\; T}{\sum\limits_{k = {- \frac{T}{2}}}^{\frac{T}{2}}{\Phi_{VV}\left( {\mathbb{e}}^{j{({\omega - \frac{2\pi\; k}{T}})}} \right)}}}}\end{matrix} & (20)\end{matrix}$

In equation (20), the fact that Φ_(VV)(e^(jω)) has a period of 2π hasbeen resorted to, in obtaining the second line.

The analysis above leads to three meaningful interpretations of thesecond term Y[n]=X[n]V_(in)[n] of Δ_(in)[n] in equation (15), for largeenough T:

1) Φ_(YY)(e^(jω)) is not a function of frequency, that is,Y[n]=V_(in)[n]×[n] is a discrete-time white noise. See FIG. 7 (d).

2) Φ_(YY)(e^(jω)) is half the input signal energy. Therefore, an inputsignal with larger energy leads to a higher white noise floor of FIG. 7(d), making it harder to extract Δ from Δ_(in)[n] of equation (15). Thisexplains why foreground calibration is much faster than backgroundcalibration. In foreground calibration, V_(in)[n]=0, and hence the noisefloor is zero, so we need much less time for convergence. In contrast,in background calibration, since normal ADC operation is not interruptedand V_(in)[n]≠0, more calibration cycles are needed to average out largenoise X[n]V_(in)[n], resulting in long convergence time.

3) The amplitude of the noise floor Φ_(YY)(e^(jω)) has no dependence onT. Therefore, increasing pseudo-random signal period T will not helpreduce noise floor.

Combining the white noise √{square root over (Φ_(YY)(e^(jω)))} andsignal ℑ{Δ·u[n]} of equation (16), the overall frequency domainrepresentation of Δ_(in)[n] is shown in FIG. 8. The signal amplitude isequal to the noise amplitude at ω₀. Since noise directly affected byV_(in)[n] is rather strong compared to signal, ω₀ is quite small.Therefore, in the vicinity of ω₀, ω<<1 and ℑ{Δ·u[n]} of (16) can bemodeled as a −20 dB/dec line, for Δ/(1−e^(jω))≅−Δ/(jω).

From the analysis above and FIG. 8, it can be seen that the function ofΔ-extraction block 640 of FIG. 6 is essentially to extract Δ out of thenoise floor in frequency domain. In other words, the problem ofdesigning a better Δ-extraction block has just been transformed into afilter design problem.

As mentioned earlier, convergence time is determined by the Δ-extractionblock. Therefore, attaining faster convergence within a givencalibration accuracy means designing a discrete-time LPF with abandwidth high enough to settle fast (for convergence time) but lowenough to reject the white noise (for accuracy). The correctness of thefilter picture was shown in Exhibit 2 of the '739 provisionalapplication, by providing that the widely used iterative method forextraction is equivalent to the 1st order IIR LPF. As noted in paragraph[0001], the '739 provisional application (including all Exhibitsthereto) is incorporated herein by reference in its entirety as thoughfully set forth.

Building upon the filter-design notion described above, the fastconvergence solution implemented in some embodiments of the presentdisclosure can be conceptualized.

Based on the frequency domain representation of Δ_(in)[n] in FIG. 8, thetrade-off that must be faced when deciding the LPF bandwidth can beseen. If the bandwidth is too small, the final convergence will beaccurate rejecting more noise, but it will take long for the LPF outputto converge. If the bandwidth is too large, convergence will be faster,but more noise filtered in undermines the calibration accuracy.Convergence time trades off with calibration accuracy, when bandwidth isthe design parameter. Therefore, in high resolution ADC applicationswhere calibration accuracy requirement is stringent, correlation-baseddigital background calibrations exhibit a long convergence time.

The fast convergence technique described in the present disclosure ismade possible by relaxing the tradeoff between convergence time andconvergence accuracy. In one embodiment, this is achieved byincorporating the following two features in the discrete-time IIR LPF.First, a higher-order discrete-time IIR LPF is used. Second, a bandwidthswitching scheme is used in the LPF, namely a large bandwidth duringtransient and a small bandwidth during steady state. “Large bandwidth”means a bandwidth larger than a reference value; “small bandwidth” meansa bandwidth smaller than a reference value. It is noted that convergencetime is a transient property and convergence accuracy is a steady-stateproperty.

Besides bandwidth, filter order is another design parameter one can makeuse of in the design of the discrete-time IIR LPF. For faster or moreaccurate Δ-extraction, a higher-order LPF is advantageous.

First, for the same bandwidth, a higher-order LPF rejects moreout-of-band noise, because the increased order corresponds to a steeperfrequency response at the falling edge. For example, by increasing thefilter order from 1 to 3 while maintaining the same bandwidth, theout-of-band noise energy at the LPF output is reduced by 80%, and thetotal noise energy at the LPF output is reduced by 40%. In general,total noise energy is equal to the in-band noise energy plus out-of-bandnoise energy. Since the signal energy is concentrated at low enoughfrequencies, the signal energy loss due to the increased order isnegligible. Overall, for the same bandwidth, while the convergence speedremains the same, a higher order LPF rejects more noise, achievinghigher convergence accuracy.

Alternatively, a scenario may be considered where the final targetcalibration accuracy is given. In other words, the out-of-band noiseenergy an LPF is to reject is fixed, in this scenario. In such a case, ahigher-order LPF can have a higher bandwidth, and hence, will exhibitfaster convergence. For example, the bandwidth of 3rd-order LPF can beset approximately twice that of the 1^(st)-order LPF, thereforeincreasing convergence speed by a factor of 2.

The advantage of a higher-order IIR LPF is thus shown, for attainingfaster convergence or higher accuracy. Too higher an order (>10),however, will not be proportionally effective, because in-band noisedominates in such high-order filters. Considering the efficacy of noisereduction, the best choice of the discrete-time IIR LPF order would bebetween 3 and 5. As discrete-time filters are used, using filter ordersbetween 3 and 5 incurs only minimum digital circuit cost.

In the above-described embodiments, introducing the filter order asanother design parameter has relaxed the tradeoff between convergencespeed and calibration accuracy, hence increasing convergence speed for agiven accuracy.

FIG. 9 illustrates a 3rd order discrete-time IIR LPF that incorporates abandwidth switching scheme. In the illustrated embodiment, another moredirect way of relaxing the tradeoff is implemented, namely: utilizationof a larger bandwidth during the calibration start-up (transient) anduse of a smaller bandwidth near & during the final convergence(steady-state).

This technique is based on the notion that the convergence speed is whatmatters during transient, and the convergence accuracy (error) is whatmatters during steady state. During calibration startup, in order toachieve a faster convergence speed, a large bandwidth is used. Duringthis phase, although more noise is let through because of the largerbandwidth, the convergence accuracy is not a concern during this earlystage of the calibration. Only after a calibration mid-point is reached,a smaller bandwidth is used to reduce steady-state convergence errors.By utilizing this adaptive bandwidth scheme, both convergence speed andconvergence accuracy may be simultaneously enhanced.

The bandwidth switching described above can be cost-efficientlyimplemented in discrete-time filters by simply altering multiplicationcoefficients, as shown in FIG. 9 for a 3^(rd)-order LPF. The extracircuitry cost is merely simple combinational logic gates and a counterused to determine when to execute the switching.

In sum, in section II of the present disclosure methods and systems havebeen described for fast convergence or acceleration of correlation-basedbackground calibration. The digital fast-convergence technique describedin the present disclosure as a cost-effective way of acceleratingcorrelation-based background calibration was made possible by a changeof view on the mismatch extraction process (a central step in anycorrelation-based digital background calibration) from the time-domainangle to the frequency-domain angle. This allowed the design of themismatch extraction algorithm to be treated as a filter design problem.Subsequently, designing a higher-order filter incorporating anopportunistic bandwidth switching scheme led to the fast convergence.

Although the above fast-convergence methods and systems were describedin the context of capacitor mismatch errors, these methods and systemscan be applied to errors caused by any other types of nonidealities,including but not limited to insufficient amplifier gain and inputoffsets.

It is contemplated that the subject matter described herein may beembodied in many forms. Accordingly, the embodiments described in detailbelow are illustrative embodiments, and are not to be consideredlimitations. Other embodiments may be used in addition or instead.

The components, steps, features, objects, benefits and advantages thathave been discussed are merely illustrative. None of them, nor thediscussions relating to them, are intended to limit the scope ofprotection in any way. Numerous other embodiments are also contemplated,including embodiments that have fewer, additional, and/or differentcomponents, steps, features, objects, benefits and advantages. Thecomponents and steps may also be arranged and ordered differently.

The phrase “means for” when used in a claim embraces the correspondingstructures and materials that have been described and their equivalents.Similarly, the phrase “step for” when used in a claim embraces thecorresponding acts that have been described and their equivalents. Theabsence of these phrases means that the claim is not limited to any ofthe corresponding structures, materials, or acts or to theirequivalents.

Nothing that has been stated or illustrated is intended to cause adedication of any component, step, feature, object, benefit, advantage,or equivalent to the public, regardless of whether it is recited in theclaims.

In short, the scope of protection is limited solely by the claims thatnow follow. That scope is intended to be as broad as is reasonablyconsistent with the language that is used in the claims and to encompassall structural and functional equivalents.

1. A background calibration method for calibrating a pipelined Analog-to-Digital Converter (ADC), the pipelined ADC having at least a first capacitor C₁ and a second capacitor C₂, the method comprising: measuring a mismatch between C₁ and C₂ to determine a capacitor mismatch value that represents the mismatch, by passing a precalibration digital output D_(out) of the pipelined ADC through a capacitor mismatch information extraction path in a background correlation loop and performing commutated feedback capacitor switching (CFCS) in the background correlation loop; and using the measured capacitor mismatch value to determine an error in D_(out) that is caused by the capacitor mismatch, and calibrating out the error by subtracting the error from D_(out), in a digital calibration path within the background correlation loop.
 2. The method of claim 1, wherein capacitor mismatch is assumed only in the MSB (most significant bit) stage of the pipelined ADC, and CFCS is performed only during the MSB stage.
 3. The method of claim 2, wherein the act of performing commutated feedback capacitor switching in a background correlation loop comprises selecting, during a charge transfer phase of the MSB stage, either C₁ or C₂ as a feedback capacitor based on a digital decision d₁ on the MSB that is determined in a preceding sampling phase.
 4. The method of claim 3, wherein the act of performing commutated feedback capacitor switching in a background correlation loop comprises selecting between a first CFCS mode and a second CFCS mode, and performing the selected mode; wherein the ADC transfer curve for the first CFCS mode is different from the ADC transfer curve for the second CFCS mode; and wherein the distance between the two different ADC transfer curves is proportional to Δ.
 5. The method of claim 4, wherein the pipelined ADC is a 1 bit-per-stage pipelined ADC; wherein in the first CFCS mode, C₁ is selected as feedback capacitor if d₁=0 and C₂ is selected as feedback capacitor if d₁=1; and wherein in the second CFCS mode, C₂ is selected as feedback capacitor if d₁=0 and C₁ is selected as a feedback capacitor is d₁=1.
 6. The method of claim 5, wherein wherein the capacitor mismatch value Δ is given by: Δ≡(C₁/C₂)−1; wherein when in the first CFCS mode is selected and performed, C₁ is selected as feedback capacitor if d₁=0 and C₂ is selected as feedback capacitor if d₁=1, and the digital output D_(out) is given by: $\begin{matrix} {D_{out} = \left\{ \begin{matrix} {{\left( {1 - {\Delta/2}} \right)V_{in}} - {\left( {\Delta/2} \right){V_{REF}\mspace{34mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\ {{\left( {1 + {\Delta/2}} \right)V_{in}} - {\left( {\Delta/2} \right){V_{REF}\mspace{34mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 1} \right\rbrack}}} \end{matrix} \right.} \\ {{= {V_{in} + {\left( {\Delta/2} \right)\left( {{V_{in}} - V_{REF}} \right)}}};} \end{matrix}$ and wherein when in the second CFCS mode is selected and performed, C₂ is selected as feedback capacitor if d₁=0 and C₁ is selected as a feedback capacitor is d₁=1, and a residue voltage V_(RES) of the MSB stage is given by: $V_{RES} = \left\{ \begin{matrix} {{\left( {2 + \Delta} \right)V_{in}} + {\left( {1 + \Delta} \right){V_{REF}\mspace{31mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 0} \right\rbrack}}} \\ {{{\left( {2 - \Delta} \right)V_{in}} - {\left( {1 - \Delta} \right){V_{REF}\mspace{40mu}\left\lbrack {{{for}\mspace{14mu} d_{1}} = 1} \right\rbrack}}},} \end{matrix} \right.$ and the digital output D_(out) is given by: D _(out) =V _(in)−(Δ/2)(|V _(in) |−V _(REF)).
 7. The method of claim 6, wherein the act of extracting the capacitor mismatch value Δ in a background correlation loop comprises: randomly choosing one mode between the first CFCS mode and the second CFCS mode, with equal probability for each input sample; creating a data sequence consisting of the resulting ADC outputs, wherein each output is multiplied by 1 if the first CFCS mode was used and by −1 if the second CFCS mode was used; and time-averaging the data sequence.
 8. The method of claim 4, wherein the pipelined ADC is a 1.5 bit-per-stage pipelined ADC; wherein in the first CFCS mode, C₁ is selected as feedback capacitor if d₁=01 and C₂ is selected as feedback capacitor if d₁=00 or d₁=10, and wherein in the second CFCS mode, C₂ is selected as a feedback capacitor if d₁=01 and C₁ is selected as a feedback capacitor if d₁=00 or d₁=10.
 9. The method of claim 1, wherein the act of extracting the capacitor mismatch value Δ comprises: passing a pre-calibration ADC output D_(out)[n] through a capacitor mismatch information extraction path P2 in the background correlation loop; in the path P2, multiplying D_(out)[n] by a pseudo-random variable X[n], and a function f(D_(out)[n]); and transmitting X[n] D_(out)[n]f(D_(out)[n]) through a Δ extraction block, wherein the Δ extraction block is a discrete-time infinite impulse response low pass filter.
 10. The method of claim 1, wherein capacitor mismatch is assumed in one or more stages of the pipelined ADC other than the MSB (most significant bit) stage, and CFCS is performed during each of said one or more other stages.
 11. The method of claim 1, wherein the pipelined ADC is an m-bit-per-stage pipelined ADC having 2^(m) capacitors C₁, C₂, . . . , C₂ ^(m) in each stage, and wherein the method further comprises: for each k=1, 2, 3, . . . 2^(m)−1, extracting a capacitor mismatch value Δ_(k) between C_(k) and C_(k+1) by performing commutated feedback capacitor switching (CFCS) in a background correlation loop; and using the extracted value Δ_(k) to calibrate out errors caused by the capacitor mismatches, for all k=1, 2, 3, . . . 2^(m)−1, by subtracting the errors from the digital output D_(out) of the pipelined ADC.
 12. The method of claim 11, wherein for each k, the act of extracting the capacitor mismatch value Δ_(k) comprises: selecting between a first CFCS mode and a second CFCS mode, wherein in the first CFCS mode, C_(k) is selected as a feedback capacitor if d₁ is even, and C_(k+1) is selected as a feedback capacitor if d₁ is odd; and wherein in the second CFCS mode, C_(k+1) is selected as a feedback capacitor if d₁ is odd, and C_(k) is selected as a feedback capacitor if d₁ is even.
 13. The method of claim 11, wherein the acts of extracting a capacitor mismatch value Δ_(k) between C_(k) and C_(k+1) and using the extracted value Δ_(k) to calibrate out errors comprise, for each input sample and time index n: selecting k and decide which Δ_(k) is to be extracted, using a pseudo-random signal X_(cap)[n] whose values are 1, 2, 3 . . . , (2^(m)−1), with equal probability; selecting between the first CFCS mode and the second CFCS mode for that k, using another pseudo-random signal X_(mode)[n] whose values are +1 and −1, with equal probability; and X_(mode)[n] D_(out)[n]f(D_(out)[n]) go through the k^(th) LPF; and extracting Δ_(k) from the output of the k^(th) LPF; and using Δ_(k) to digitally calibrate out the error caused by capacitor mismatch between C_(k) and C_(k+1).
 14. A system for background calibrating a pipelined ADC, the pipelined ADC having a sampling capacitor C₁ and a feedback capacitor C₂, the system comprising: circuitry configured to measure a value Δ of a capacitor mismatch between the sampling capacitor C₁ and the feedback capacitor C₂ by performing commutated feedback capacitor switching during a charge transfer phase of the pipelined ADC, the circuitry further configured to use the measured value of the mismatch to determine an error in a precalibration digital output D_(out) of the pipelined ADC, caused by the capacitor mismatch, and to calibrate the ADC by subtracting the capacitor mismatch error from the digital output D_(out), in a digital calibration path within a background correlation loop in the system.
 15. The system of claim 14, wherein the circuitry further comprises: a pseudo-random number generator configured to generate a pseudo-random variable X[n], where n is the number of input samples to the ADC; an analog-to-digital conversion module configured to generate a pre-calibration ADC output Dout[n] from an analog input voltage V_(in) of the pipelined ADC; a Δ extraction module configured to process the variable X[n] and the output Dout[n] to extract the value Δ of the mismatch between C₁ and C₂, the A extraction module including a discrete-time infinite impulse response low-pass filter (IIR LPF) configured to output a DC average of X[n] Dout[n]; and a digital calibration module configured to receive as input the capacitor mismatch value Δ and the pre-calibration output Dout[n], the digital calibration module further configured to calibrate the output Dout[n] by subtracting therefrom the error caused by the capacitor mismatch value Δ.
 16. The system of claim 15, wherein the analog-to-digital conversion module includes a control switch configured to select between a first CFCS mode and a second CFCS mode, based on the value of the pseudo-random variable X[n].
 17. The system of claim 15, wherein the analog-to-digital conversion module further includes one or more comparators configured to generate a digital decision for the input voltage V_(in) for one or more stages of the pipelined ADC.
 18. A method of increasing convergence speed during a digital background calibration of a pipelined ADC, the method comprising: using a low pass filter (LPF) of order higher than one, when performing discrete-time low-pass filtering to extract a mismatch value between a first component and a second component of the pipelined ADC; and utilizing a bandwidth switching scheme in which a bandwidth larger than a reference value is used during calibration start-up so as to increase convergence speed, then the bandwidth is decreased after calibration mid-point so as to increase convergence accuracy during steady state.
 19. The method of claim 18, wherein the first component is a sampling capacitor and the second component is a feedback capacitor.
 20. The method of claim 18, further comprising the act of utilizing a bandwidth switching scheme in which a bandwidth larger than a reference value is used during calibration start-up so as to increase convergence speed, then the bandwidth is decreased after calibration mid-point so as to increase convergence accuracy during steady state. 